Is there a way of seeing how Lattice Diamond implements an expression?
My (as yet untested) VGA pattern generator Verilog source code has an expression “CounterY<10’d480”. With my programmer hat on, the ‘obvious’ way to implement that is with a 10-bit adder (CounterY+(10’d-480)) and seeing if there’s a carry. But, since
10’d480=10’b0111100000 and I know that CounterY never exceeds 10’d524=10’b1000001100,
if I were doing this with 74xx-series chips I’d implement it as
(CounterY==1’b0) && (Counter[8:5]!=4’b1111)
So I’m wondering if the latter expression would take up less space in the FPGA than the former. (It fits anyway, so I’m only asking in anticipation of some future time when I’ll want to squeeze as much as possible into my A1.)