I have some code in SpinalHDL to drive a 74HC595 shift register but not in Verilog.
So I will have a go at a Verilog version.
Your top level module will need to declare the clock, data and latch pins, as well as the system clock:
module top (
// Add logic here
For the logic, you will need a shift register and you will normally set shiftout_data to the most significant bit of that if you are shifting MSB first or the LSB if LSB first. Lets assume MSB first:
reg [7:0] shift_reg;
assign shiftout_data = shift_reg;
You will need to set the 74HC595 clock. Lets assume for the moment we just set it to the 16Mhz TinyFPGA BX clock:
assign shiftout_clock = clk_16Mhz;
You will need to set the 74HC795 latch high:
assign shiftout_latch = 1;
And then every clock cycle, you will want to shift a bit out:
always @(posedge shiftout_clock) shift_reg <= shift_reg << 1;
What we have not yet done is set the shift register to the data we want to shift out.
One way to do this is to have a bit_counter that we increase by one each time we shift a bit out, so change that always block to:
reg [2:0] bit_counter = 0;
reg [7:0] data_out = 8'h42;
always @(posedge shiftout_clock) begin
shift_reg <= shift_reg << 1;
bit_counter <= bit_counter + 1;
if (bit_counter == 7) shift_reg <= data_out;