A2: Dedicated I/O pin for PLL input


#1

I’m lost in the Lattice docs.

I found this in the Clock PLL Design and Usage Guide:

The CLKI signal can come from a dedicated dual-purpose I/O pin, from any I/O pin,
or from routing. The dedicated dual-purpose I/O pin provides a low skew input path and is the recommended > source for the PLL.

So, I’d like to hook my external clock source to the dedicated dual-purpose I/O pin. Does anyone know which one that is?


#2

Pins 5, 6, 10, or 11 on the TinyFPGA A1 or A2 boards are what you want. I’ll be making a pin reference card for this stuff in the future.


#3

Here’s a first draft of an A-series reference card. These reference cards would be included with each TinyFPGA board. Similar to the cards included with Teensy boards. What kind of information would you like to see?


#4

This is a great idea. Typo on pin 10 or 11, both labeled PCLKC0_0 (one should be T?) Title should be “AX,” not “AX1”?

So, here’s my perspective, which may represent a portion of your market/audience. I come from an embedded software background: FPGA’s got handled by a guy in another cube. For instance, I had found these mappings through a pinout spreadsheet created by the Diamond software (nowhere as nice/convenient as your diagram), but the function of some of the pins escapes me. Here are some example questions to give you an idea of where people might be coming from:

What is the function of the SN/DONE/CSSPIN/PROGRAMN/JTAGENB pins (guessing the last is a JTAG enable active-low)?

You mention above that the low-skew PLL inputs are on pins 5, 6,10, or 11. How would I tell that from this diagram? Why not 1,2,16,17,21 or 22?

You may have already covered this in the documentation somewhere. I’m sure they’re all in the Lattice docs somewhere, but those are fragmented across multiple PDFs, making blind searching difficult.


#5

Hi, Ted.
As for JTAGENB, I think it’s ‘usually’ programmed to be general purpose I/O (and then the 4 JTAG pins are for JTAG) but it can be programmed to an active-high enable for the JTAG pins.

I’ve written .v and .lpf files to use the JTAG pins as I/O but haven’t tested it yet, so I may be completely wrong!

Here’s my .lpf (in full):
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
SYSCONFIG JTAG_PORT=DISABLE ;
SYSCONFIG MUX_CONFIGURATION_PORTS=ENABLE ;
LOCATE COMP “pin1” SITE “13” ;
LOCATE COMP “pin2” SITE “14” ;
LOCATE COMP “pin3_sn” SITE “16” ;
LOCATE COMP “pin4_mosi” SITE “17” ;
LOCATE COMP “pin5” SITE “20” ;
LOCATE COMP “pin6” SITE “21” ;
LOCATE COMP “pin7_done” SITE “23” ;
LOCATE COMP “pin8_pgmn” SITE “25” ;
LOCATE COMP “pin10_sda” SITE “27” ;
LOCATE COMP “pin11_scl” SITE “28” ;
LOCATE COMP “pin12_tdo” SITE “1” ;
LOCATE COMP “pin13_tdi” SITE “32” ;
LOCATE COMP “pin14_tck” SITE “30” ;
LOCATE COMP “pin15_tms” SITE “29” ;
LOCATE COMP “pin16” SITE “4” ;
LOCATE COMP “pin17” SITE “5” ;
LOCATE COMP “pin18_cs” SITE “8” ;
LOCATE COMP “pin19_sclk” SITE “9” ;
LOCATE COMP “pin20_miso” SITE “10” ;
LOCATE COMP “pin21” SITE “11” ;
LOCATE COMP “pin22” SITE “12” ;

and here’s the start of my .v:
module TinyFPGA_A1 (
inout pin1,
inout pin2,
inout pin3_sn,
inout pin4_mosi,
inout pin5,
inout pin6,
inout pin7_done,
inout pin8_pgmn,
//inout pin9_jtgnb, Pull high for programming, low to use.
inout pin10_sda,
inout pin11_scl,
output pin12_tdo,
input pin13_tdi,
input pin14_tck,
input pin15_tms,
inout pin16,
inout pin17,
inout pin18_cs,
inout pin19_sclk,
inout pin20_miso,
inout pin21,
inout pin22
);

Of course, if you want to program the FPGA in-circuit, whatever your circuit is that’s connected to the 4 JTAG pins musn’t “get in the way”, and you’ll have to pull the JTGNB high to program, and pull it low (and unplug the programmer?) to use the I/Os.

I should probably mention that this was for an A1. Dunno it it’d be the same for the A2.


#6

Thanks for the great explanation @BruceMardle! @ted.yapo, I have an updated version of the reference card. I sub-divided the dual-function pins into the respective functions.

I’ll add current ratings and some other information on the back based on feedback from Twitter.