Async memory not initializing properly unless output is registered


#1

I just recently picked up a TinyFPGA AX2 to learn verilog.
Wish I did this a few years ago, when there was more activity here!
As a project, I’m implementing a 4-bit cpu (nibbler).

There’s something strange that I don’t understand with my implementation of asynchronous ROM.
Here’s the code:
//The 28C64 Program ROM chip with WEn high and OEn and CEn low.
wire [7:0] PROM_Output;
reg [7:0] Program_ROM [0:4095];
initial begin
//$display(“Loading rom.”);
$readmemh(“guess.hex”, Program_ROM);
end
//RJA making this Asynchronous
assign PROM_Output = Program_ROM[Program_Address];

Program_Address is, for now, just a very slow counter.

At start up, Program_Address is 0, but PROM_Output is also zero and not Program_ROM[0]
I’ve tried some things, but can’t get that to work right.
After the counter increments, it does show the correct output, but not before.

However, it does work if I then send the output to a latch register like this:
//The 74HCT377 Octal D Flip-Flop with Clock Enable
reg [7:0] Fetch;
always @ (posedge clk)
begin
Fetch <= PROM_Output;
end

Can anyone explain this behavior?


#2

Turned out there was even worse trouble when I tried to combine 8 async signals with 4 sync signals to form the Data Address Bus. The Lattice compiler choked on that.

So, gave up on that and now have the Program ROM with register output but clocked by the main clock.
The other chips will be clocked by a divided down version of the main clock.
So, it should have the same output as Nibbler, just not exactly the same way.