I just recently picked up a TinyFPGA AX2 to learn verilog.
Wish I did this a few years ago, when there was more activity here!
As a project, I’m implementing a 4-bit cpu (nibbler).
There’s something strange that I don’t understand with my implementation of asynchronous ROM.
Here’s the code:
//The 28C64 Program ROM chip with WEn high and OEn and CEn low.
wire [7:0] PROM_Output;
reg [7:0] Program_ROM [0:4095];
//RJA making this Asynchronous
assign PROM_Output = Program_ROM[Program_Address];
Program_Address is, for now, just a very slow counter.
At start up, Program_Address is 0, but PROM_Output is also zero and not Program_ROM
I’ve tried some things, but can’t get that to work right.
After the counter increments, it does show the correct output, but not before.
However, it does work if I then send the output to a latch register like this:
//The 74HCT377 Octal D Flip-Flop with Clock Enable
reg [7:0] Fetch;
always @ (posedge clk)
Fetch <= PROM_Output;
Can anyone explain this behavior?