Async reset using PUR


Hi All,

I’m fairly new to FPGA and Verilog and am trying to get the internal asynchronous reset working on power-up. Some Lattice documentation states there is a built-in PUR (Power Up Reset) in all Lattice FPGAs which is asserted (active-low) for a time following startup. However, it’s not clear how I should use this resource in my design. I have a number of blocks of code implementing an async active-low reset in the following manner:

always @(posedge clk or negedge nrst) begin
if (0 == nrst)
counter <= 25’b0;
else begin
counter <= counter + 25’b1;

When I synthesise this code, the Lattice tools work out that nrst is an active-low reset and assign it to the GSR Global Set/Reset net. However, in the example above, the counter wouldn’t increment when programmed into my Tiny FPGA. I presume this is because the nrst signal remains low indefinitely because it isn’t being driven by the PUR resource. FWIW: I’m bringing nrst out as an input in the top-level and diamond doesn’t assign a pin to it.

Reading the Lattice documentation (link below) on GSR and PUR hasn’t really helped me. While they mention a special “PUR” component, it would appear this is for use in simulation and not for synthesizable code.

Any advice on this would be great!


Can you post or paste your whole Verilog file? I think it might just be a simple mixup between GSR and PUR.