I have been working on a design which uses the hardened User Slave SPI on the Machxo2 and need some pointers/help. The design simulates as expected using Active-HDL but in hardware I’m obviously missing something as it appears to think that the transfer has completed on the first rising edge for the SPI clock. I am using a Raspberry Pi Zero to drive the SPI and I have tried a long list of different transfer speeds with no luck. No matter what the SPI or wishbone speed is, I can see on the first rising clock edge the SPISR register negates the TIP field (Transmission in Progress) which naturally cause my FSM to restart and nothing good happens from there. The expected behavior and what is shown in the simulator is the TIP remains high as long as the SPI Chip Select is asserted (low).
Since it works in simulation, it seems it is an electrical issue. However, the 3.3v rail and signals all look ok. I looked at them directly on the RPi and down stream at the FPGA and they don’t look too concerning to me. There is some softening of the signal edges but that is expected. No real overshoot or ringing, if anything the clock rising time is a little long for my liking. So I’m scratching my head a bit. Speed of the SPI seems to have no effect, I have tried many different builds with fast and slow SPI and/or Wishbone clock rates, etc. all with no real change in behavior. For all these tests I’m using a Raspberry Pi Zero W connected to a custom PCB which has the AX2 board on it. I have tried powering it from the RPi Zero and from an independent supply with no change. Some other things of note which I think should be fine, is that I’m using the on board oscillator (OSCH). It isn’t the most accurate clock with a +/-5% rating but shouldn’t really matter for what I’m using it for.
I have a test build here, you will need a lattice diamond license to run it:
the included README has instructions on what is there and how to run the test bench. The FSM basically implements what is in their document with one change. The reference FSM doesn’t work if you have a chip select asserted more then one cycle from the SPI clock, so I added a step to wait for TX ready under that condition. (See: Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Reference Guide, TN1246, Figure 18)
Any advise would be appreciated. I haven’t yet given up on the User SPI Slave EFB but may have to just use my own SPI slave. I can upload scope captures if needed but don’t have access to do so in the forums.