BX2 Eg.: simpleuart.v: question on verilog code


#1

Hi, I’m trying to understand the operation of simpleuart peripheral in the official example given as part of picosoc. Here is the relevant code:

always @(posedge clk) begin
		if (!resetn) begin
			recv_state <= 0;
			recv_divcnt <= 0;
			recv_pattern <= 0;
			recv_buf_data <= 0;
			recv_buf_valid <= 0;
		end else begin
			recv_divcnt <= recv_divcnt + 1;
			if (reg_dat_re)
				recv_buf_valid <= 0;
			case (recv_state)
				0: begin
					if (!ser_rx)
						recv_state <= 1;
					recv_divcnt <= 0;
				end
				1: begin
					if (2*recv_divcnt > cfg_divider) begin
						recv_state <= 2;
						recv_divcnt <= 0;
					end
				end
				10: begin
					if (recv_divcnt > cfg_divider) begin
						recv_buf_data <= recv_pattern;
						recv_buf_valid <= 1;
						recv_state <= 0;
					end
				end
				default: begin
					if (recv_divcnt > cfg_divider) begin
						recv_pattern <= {ser_rx, recv_pattern[7:1]};
						recv_state <= recv_state + 1;
						recv_divcnt <= 0;
					end
				end
			endcase
		end
	end

The state machine around recv_state is initially (upon reset) assigned 0. From there, it can go to state 1 and subsequently to state 2. These are explicit assignments, and not an ‘increment’ operation onrecv_state. The only increment operation on recv_state which can take it to a value other that 1 or 2 is in the default clause. From state 2, it can only go to state 0.

As far as I understand, I do not see any other conditions that can trigger the default clause. So in effect, this state machine would not trigger the default clause. I also noticed that the main shift logic for receiving is happening in the default clause. So, how will the reception work ?


#2

The default case handles states 2 - 9 , which process the 8 bits, and then go to state 10. You might have confused the 10 state with 2’b10.


#3

Correct, I overlooked the base of the number. Thank you so much for pointing it out!