I’m somewhat familiar with process, having done Verilog design and simulation many years ago.
I’m not familiar with the Lattice tools, though, which seem to be based on Mentor.
I opened template_a2 and TinyFPGA_A2.v and changed the target to LCMXO2-256HC.
I wanted to simulate the Verilog of this example just to verify everything was functional, I expected to see the counter waveforms in the simulator. From Diamond, I can use Tools / Modelsim Lattice Edition, which opens a new window. If I select Simulation / Start Simulation, it brings up another dialog with a tree view of library items. The OK button is grayed out, though.
In the transcript, I find:
# Reading pref.tcl
# Load canceled
I must be missing something. Is there a full walk-through tutorial for this tool chain?
I also tried Diamond / Tools / Simulator WIzard. I created a project name, chose RTL as the process stage, I did not add a test bench since this LED blink should operate standalone - without any external input. It went through a Parse HDL Files for simulation, and indicated TinyFPGA_A2 was the Top Module.
There was a summary dialog with Finish button.
The simulator runs, and shows waveforms. The only signal is the clock - clk.
In the transcript:
# ** Warning: (vsim-3722) C:/Data/DEV/FPGA/TinyFPGA/TestProject/TinyFPGA_A2.v(58): [TFMPC] - Missing connection for port ‘SEDSTDBY’.