(See update below)
When attempting to upload/build my project, I get an error with no indication of where it came from:
ERROR: Missing edge-sensitive event for this signal! scons: *** [hardware.blif] Error 1
Running “apio build -v” in the terminal gives me a tiny bit more information
3.7.7. Executing PROC_DFF pass (convert process syncs to FFs) ERROR: Missing edge-sensitive event for this signal! scons: *** [hardware.blif] Error 1
I’ve looked online for the cause of the error and haven’t found anything besides this unanswered yosys issue. Usually I’d use process of elimination to find what the offending code is, unfortunately my verilog file is over 700 lines long as it’s been generated from a netlist.
I have little experience with the toolchain and have no idea how to coax more information out of it.
If anyone knows how this error comes about, or how to find the line number/component name of the cause, it would be greatly appreciated. Knowing either of these would probally help me enough to fix it.
Ok, much debugging later I think I fixed it. I grep-ed for the error message, found it in yosys, downloaded the source, grep-ed again, found code that generates the message in passes/proc/proc_dff.cc, modified print statements to tell me what the element was, installed clang & 'gang, compiled yosys, replaced the executable files in the .apio folder, and ran it.
Almost everyone of my flip-flops caused the error, apparently code similar to the peice below would cause the “missing edge-sensitive event” error.
reg flipflop = 0; always @(posedge thing1 or posedge thing2 or posedge thing3) begin if(thing1 || thing2) flipflop <= 0; else if(thing3) flipflop <= 1;
I’m a Verilog newbie but the code above appears valid to me, the fix was to change the above code to the below code
reg flipflop = 0; always @(posedge thing1 or posedge thing2 or posedge thing3) begin if(thing1 || thing2) flipflop <= 0; else flipflop <= 1;
This now gives me a “Multiple edge sensitive events” error which is fixed with the below code
reg flipflop = 0; always @(posedge thing1 or posedge thing2 or posedge thing3) begin if(thing1) flipflop <= 0; else if(thing2) flipflop <= 0; else flipflop <= 1;
Again, I believe all the example code works is identical behavior, valid Verilog (correct me if I’m wrong), which means yosys likes it a certain way. If this is the case, I’ll report it as a yosys bug. Anyway, it builds/uploads now (I had to reinstall the dev enviorment because I messed up something in yosys), still doesn’t behave how I want it to, but I guess thats my problem