Diamond/ModelSim post-route timing simulation problems


#1

I’m new to TinyFPGA, but have a solid electrical engineering background and were designing ASICs 20 years back - so my experience has likely diluted over time.
I’m working on a Tiny FPGA project for sensors and actuators where each tinyFPGA provides an 8 bit digital sensor input, and a 4 actuators output with different modes of operation (on/off, PWM, and pulses) - they are serially interconnected in a ring using the WS2811 pixel "protocol, and intercepted by a ESP32.
I have successfully built a pretty decent test bench for system simulation which successfully verifies 3 interconnected instances of the design at RTL level (takes 4 hours to complete with my brand new RYZEN 7 machine:-).
Next I want to do is to do post-routing simulation to verify the timing - and here I get stuck. I’m using Lattice Diamond and the “build in” ModelSim.
I want all the testbench logic to be RTL simulated while the actual FPGA design instances to be post-routing/time simulated.
The .mdo script for modelsim generated by Lattice Diamond looks like this:

if {![file exists “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/timing/timing.mpf”]} {
project new “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/timing” timing
project addfile “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.vo”
project addfile “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/genericIOSatelite_TB.v”
vlib work
vdel -lib work -all
vlib work
vlog +incdir+C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1 -work work “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.vo”
vlog +incdir+C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2 -work work “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/genericIOSatelite_TB.v”
} else {
project open “C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/timing/timing”
project compileoutofdate
}
vsim -L work -L pmi_work -L ovi_machxo2 +transport_path_delays +transport_int_delays genericIOSatelite_TB -sdfmax /genericIOSatelite_TB/DUT0=C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf
view wave
add wave /*
run 1000ns

Where “genericIOSatelite_impl1_vo.vo” is my routed and placed FPGA design, “genericIOSatelite_TB.v” is my testbench, “genericIOSatelite_impl1_vo.sdf” is the timing database for my FPGA design and “/genericIOSatelite_TB/DUT0” is one out of three testbed instantiations of the FPGA design (eventually I would want all three simulated with timing, but one problem at the time).

Now I get the following errors:

Loading instances from C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf
** Error (suppressible): (vsim-SDF-3250) C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf(7071): Failed to find INSTANCE ‘SLICE_303’.
** Error (suppressible): (vsim-SDF-3250) C:/Users/jonas/OneDrive/Projects/ModelRailway/GenericJMRIdecoder/hardware/Satelites_CRC_2/impl1/genericIOSatelite_impl1_vo.sdf(7082): Failed to find INSTANCE ‘SLICE_304’.

And 100’ds of more errors like this…
But when I look at the first error: “Failed to find INSTANCE ‘SLICE_303’” I don’t understand the issue, I can clearly see the ‘SLICE_303’ instance both in “genericIOSatelite_impl1_vo.sdf” and in “genericIOSatelite_impl1_vo.vo”:

“genericIOSatelite_impl1_vo.sdf”:

(CELL
(CELLTYPE “SLICE_303”)
(INSTANCE SLICE_303)
(DELAY
(ABSOLUTE
(IOPATH B0 F1 (635:710:786)(635:710:786))
(IOPATH A0 F1 (635:710:786)(635:710:786))
(IOPATH FCI F1 (459:514:569)(459:514:569))
)
)
)

“genericIOSatelite_impl1_vo.vo”:

SLICE_303 SLICE_303( .B0(control_7_adj_1162), .A0(cnt_9_adj_1170),
.FCI(n4958), .F1(n312));

I would very much like to get an advise on what I’m doing wrong here, using the inbuilt OSCH with 133 MHZ Freq, and with 7ns cycle time I believe it would be nice with a reassuring post-routing/placement simulation @ worst timing.

Best regards/Jonas