Error during GTKWave File Creation


#1

Greetings,

I have written a simple test bench for my module, but I’m having trouble with generating the .gtkw file. Here is my test bench:

	`timescale 1ns/1ps
module tb ();
  initial begin
	$dumpfile("top_tb.vcd");
	$dumpvars(0, t);
  end

  reg clk;
  wire pin_13, pin_12, pin_11, usbpu;

  initial begin
		clk = 1'b0;
	end

  always begin
	#31 clk = !clk;
  end

  initial #10000 $finish;

  top t (.CLK(clk), .PIN_13(pin_13), .PIN_12(pin_12), .PIN_11(pin_11), .USBPU(usbpu));
endmodule // tb

Here is the error message that I receive:

iverilog -o tob_tb.out -D VCD_OUTPUT=tob_tb "C:\Users\Michael\.apio\packages\toolchain-iverilog\vlib\cells_sim.v" Max7219_2.v counter_4.v spi_master_3.v tob_tb.v top.v
vvp tob_tb.out
VCD info: dumpfile top_tb.vcd opened for output.
gtkwave tob_tb.vcd tob_tb.gtkw
Why: No such file or directory
 
GTKWave Analyzer v3.3.77 (w)1999-2016 BSI

 
Error opening  .vcd file 'tob_tb.vcd'.
scons: *** [sim] Error 255
========================= [ ERROR ] Took 4.26 seconds =========================

top_tb.vcd seems to be generated and is present in the folder.

Does anyone have any idea why I am receiving this error?

I’m running on Windows 10. I have it working on macos. I installed GTKWave through apio install.

Thanks.


#2

Hi,

it seems like you have a typo in your filenames.

top!=tob

I assume, you already got it working?


#3

Yes, I caught that. Even with top.tb, it still gives me the error. The strange thing is that it doesn’t happen all the time. Sometimes, it will launch GTKWave. I can get it to work by running the sim from Atom, then double-clicking the output file to load it.