I have a Simple Design that seems to break when changing almost any part of the Verilog or pin mapping.
Most changes to the design seem to cause the user image to fail booting. I have narrowed it down to the amount of BRAMs I am using.
If I use 2x then the image works, if I use 1x then the image fails. If i use more than 2x then the image also fails. This can be observed by the user_led hanging at a dim brightness.
You can tell for yourself using the code here:
When ROMDEPTH is set to 512 the design boots successfully. Changing ROMDEPTH to any number >512 causes the image to fail. Changing ROMDEPTH to any number <=256 causes it to fail aswell. This corresponds the the number of BRAMs allocated by arachne-pnr…
Note that this design does not boot at all when using nextpnr.
Any tips would help a lot. I have a feeling my clock domain may be interfering with LUTs accessing the BRAMs but I’m not experienced enough to say decidedly.