Fatal error: no top model has been defined


#1

Hello,
I have built and flashed the blink example succesfully. Now I want to add another Verilog file but I get this error. I just added valid *.v file to the same directory. I understand that I need to define the top module, but I’m not sure where and what parameter needs to be written. I use Ubuntu and Atom with APIO-ide.

I’ve tracked that the yosys has -top parameter but I cannot find how to pass this parameter from APIO.

[Wed Aug  1 09:36:02 2018] Processing TinyFPGA-BX
--------------------------------------------------------------------------------
yosys -p "synth_ice40 -blif hardware.blif" -q top.v uart_tx.v
arachne-pnr -d 8k -P cm81 -p pins.pcf -o hardware.asc -q hardware.blif
hardware.blif:2: fatal error: no top model has been defined
scons: *** [hardware.asc] Error 1
========================= [ ERROR ] Took 1.30 seconds =========================

Thanks


#2

If your top module instantiates uart_tx, then the tools should deduce the top module.


#3

Ok, I tried to make simplier example with second module. This works and compiles fine.
I just had to add include in the top.v and ifdef to the morse.v module. Is this correct?

top.v

`include "morse.v"

// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
    input CLK,    // 16MHz clock
    output LED,   // User/boot LED next to power LED
    output USBPU  // USB pull-up resistor
);
    // drive USB pull-up resistor to '0' to disable USB
    assign USBPU = 0;

    morse insta_a (
      .CLK    ( CLK  ), // input
      .LED    ( LED ) // output
    );

endmodule

morse.v

`ifndef __MORSE_MODULE__
`define __MORSE_MODULE__

// look in pins.pcf for all the pin names on the TinyFPGA BX board
module morse (
    input CLK,    // 16MHz clock
    output LED   // User/boot LED next to power LED
);
    // drive USB pull-up resistor to '0' to disable USB

    ////////
    // make a simple blink circuit
    ////////

    // keep track of time and location in blink_pattern
    reg [25:0] blink_counter;

    // pattern that will be flashed over the LED over time
    wire [31:0] blink_pattern = 32'b101010001110111011100010101;

    // increment the blink_counter every clock
    always @(posedge CLK) begin
        blink_counter <= blink_counter + 1;
    end

    // light up the LED according to the pattern
    assign LED = blink_pattern[blink_counter[25:21]];

endmodule

`endif // __MORSE_MODULE__

When I remove include "morse.v" then I get error in the syntax highlighter but projects compiles and works fine.

When I remove ifndef in the morse.v and keep the include, then i get this error:
ERROR: Re-definition of module\morse’ at morse.v:5!Does this mean, that APIO or YOSYS takes all the*.v` files in the folder so I don’t have to include them?

Thanks for any tips. I would like to know the workflow nad best practices in the begining.


#4

You shouldn’t need to do the include. The error in the syntax checker can be ignored. I was thinking about writing a post about the usability of the Atom environment. One problem is the syntax error you get on instances of modules from other files, as you have seen. A second problem is that warnings flash by and disappear. Warnings need to be looked at as they often stop the design from working. The issue about --warn-no-port, that I posted about, doesn’t help with this as it generates lots of warnings. I sometimes have to use apio from the command line to see warnings. A third issue is that it is hard to scroll through the error and warning messages as the window has no scroll bar and up and down arrow do not work. But the mouse scroll wheel seem to work, so I suppose it is not too bad.


#5

The Linter errors on module instantiations seem to come and go. They have now disappeared on a couple of my projects, without me doing anything.


#6

There seems to be some information on the Linter errors on module instantiations here:

This is about the Sublime editor plugin, not Atom, but the issue seems to be the same.

I don’t like the solution of using includes everywhere just to circumvent a Linter plugin problem.


#7

You have to set the paths in the linter.

Go to File -> Settings.

Find the tab to the left for

Packages

Then find

apio-linter-verilog

Click on it’s settings button.

put a setting to the folder like this

-i"C:\\path-to-your-project\\project"

replace path-to-your-project as the projects complete path.

it should go in the Settings -> extra options box.


#8

Thanks for that. It worked, but the setting seems to be global, so if you are working on several projects, it won’t work. I suppose you could include multiple projects in the setting, but that would not work very well, particularly if there are multiple versions of the same module.


#9

You can put more than one path like this -i"C:\path1;C:\path2"

maybe there are wildcards also or put the base path to the highest folder.
I think it is searching recursively into sub folders.


#10

I had a similar issue with apio earlier today. I gave up and renamed top.v to zztop.v so it appeared last in the list of arguments to yosys (which on my machine seem to be supplied in alphabetical order). This seemed to resolve the issue, but it sure made me feel dirty.

I should probably revisit this morning’s events now that the fog of war has passed, and see what was going on in more detail.


#11

Thank you for the tips. I will get back to tinyFPGA on weekend and try bigger project.
Martin