Global Buffer Inputs


Hi There,

May I ask why the 16MHz CLK on the BX is not routed to a GBIN_ pin?
Can I use the 16MHz CLK as my system clock or do I need to buffer it somehow?




Luke has previously said that this was an oversight. From what I understand, the clock doesn’t have to go into a GBIN port in order to be routed to a global buffer line. When using the open source toolset at least, the 8 global buffered lines are automatically allocated, and in the designs I’ve been playing with these seem to be consistently allocated to the highest fan-out nets. This happens without any intervention on my part. It’s possible a few extra LUTS are burnt getting the signal to the global buffers, and maybe that introduces some small delays, but for the designs I’ve been playing with I haven’t really noticed.


Having not used lattice parts before, and not dug in on the Bx, I’m far enough out of my knowledge sphere that maybe you should ignore me completely. But typically, @gundy is right in that a clock can (sort of) come from anywhere. For instance (and assuming the architecture is similar), on the Max10 family of parts, there are a handful of clock control blocks that can take input from a handful of places and route them appropriately to a clock net. One of those possible sources is “any old net in your design,” which of course can be driven by any old GPIO.

So then what’s the necessity of the dedicated clock inputs? Timing control. Routing (any old gpio)>(any old net)>(clock control block)>(clock net) is bad news because the timings of the first two pieces are both not-necessarily-constrained and not necessarily deterministic based on the placement step. The other issue is that clock integrity is not guaranteed across a chain like that. The rule of thumb is, if you have any choice in the matter at all, an externally sourced clock should go through an onboard PLL to clean it up. The next best thing is to meticulously handle clock signal integrity on the PCB, then route it through an IO pin that handles it with due care onto an internal clock net. If you need your design internally to be phase-aligned and cycle-accurate to an external clock, PLLing it isn’t an option. If you’re trying to coordinate multiple parts on a global board-level clock, not using a clock pin could really ruin your day with weird timing problems.

In the end, most of the designs the Bx will see won’t be subject to the kinds of problems caused by not using a clock pin.