Gtkwave memory array visualization


Hi There,

I have instantiated a memory array with a constructor like this:
reg [a:0] mem [b:0]

(hopefully the synthesizer will use the BRAM cell to implement it).
How can I see the memory content in simulation?
For some reason gtkwave is not loading this memory matrix (or the tool is not dumping it in the vcd file?).



To get yosys to infer RAM, you may need to wrap it up in a module, with read/write enable and address ports - something like:

module ramblock (
  input clk, wen, ren, 
  input [$clog2(b):0] waddr, raddr,
  input [a:0] wdata,
  output reg [a:0] rdata
  reg [a:0] mem [0:b];
  always @(posedge clk) begin
    if (wen)
      mem[waddr] <= wdata;
    if (ren)
      rdata <= mem[raddr]

As to gtkwave and visualisation of block RAM - there’s some info in the Icarus+GTKWave guide here:

I’ve quoted the relevant section below for reference:

NOTE: In case you have defined arrays in your design. E.g.:

module Mem (bla, bla, bla, ...);
reg [M:0] data [0:N];

its important that you include also these lines in your initial block (for every array you defined), in order to be able to see the array signals in GTKWave:

module Test;

 integer i;
 initial begin
   $dumpvars(0, my_module_name);
   for (i = 0; i < M; i = i + 1)


Hope that helps.



Thanks a lot!
Here my memory code:

// RAM 256x16
module ram (
input CLK,
input [7:0] W_ADDR,
input [7:0] R_ADDR,
input WRITE_EN,
input READ_EN,
input [15:0] DIN,
output reg [15:0] DOUT

reg [15:0] mem [0:255];
always @(posedge CLK) begin
mem[W_ADDR] <= DIN;
if (READ_EN)
DOUT <= mem[R_ADDR];


for some reason it is not turned into BRAM.
I use the apio build command to syth the rtl.

Do you see any problem with my module?



If you don’t make much use of the RAM, Yosys might decide not to use BRAM. Make sure for write and read it all.