How to create an input pin in Verilog?


Sorry for such a ridiculously basic question, but…
How do I create an input pin in Verilog?
E.G. How would I get pin 2 of a TinyFPGA to output whatever’s on pin 1?
I’ve tried
assign pin2 = pin1;
but I when I try to build the JEDEC file, I get
WARNING - I/O Port pin2 's net has no driver and is unused.


Try changing pin1 from “inout” to “input”.

Edit: and pin2 from “inout” to “output”.


Then it gives the same warning about both pins!


Interesting, can you post your full Verilog code?


module TinyFPGA_A1 (
input pin1,
output pin2,
inout pin3_sn,
inout pin4_mosi,
inout pin5,
inout pin6,
inout pin7_done,
inout pin8_pgmn,
inout pin9_jtgnb,
inout pin10_sda,
inout pin11_scl,
//inout pin12_tdo,
//inout pin13_tdi,
//inout pin14_tck,
//inout pin15_tms,
inout pin16,
inout pin17,
inout pin18_cs,
inout pin19_sclk,
inout pin20_miso,
inout pin21,
inout pin22

// left side of board
// assign pin1 = 1’bz;
assign pin2 = pin1;
assign pin3_sn = 1’bz;
assign pin4_mosi = 1’bz;
assign pin5 = 1’bz;
assign pin6 = 1’bz;
assign pin7_done = 1’bz;
assign pin8_pgmn = 1’bz;
assign pin9_jtgnb = 1’bz;
assign pin10_sda = 1’bz;
assign pin11_scl = 1’bz;

// right side of board
//assign pin12_tdo = 1’bz;
//assign pin13_tdi = 1’bz;
//assign pin14_tck = 1’bz;
//assign pin15_tms = 1’bz;
assign pin16 = 1’bz;
assign pin17 = 1’bz;
assign pin18_cs = 1’bz;
assign pin19_sclk = 1’bz;
assign pin20_miso = 1’bz;
assign pin21 = 1’bz;
assign pin22 = 1’bz;



It should still work, though I haven’t noticed this warning before. If you upload a zip file of the whole project directory I can take a look and see if I can reproduce the warning message.


Apart from the few tweaks to the Verilog file it should be identical to
(unless that has changed since I downloaded it).


I had a similar problem and was not working because i have renamed the pins in the *.v file but not in the *.lpf file.
Check that every ping has the same name in both files.

Best regards


Thanks for the suggestion, sebasjm, but that doesn’t seem to be the problem here.


I know it’s been a few days, but I have some time to try and reproduce this issue tonight.


@BruceMardle: I tried to reproduce the warning by re-downloading the A1 template and replacing the contents of the verilog file with the code you posted. I had to fix the single quotes as the web-browser changed them to left/right single quotes. After I made that fix the project synthesized into a bitstream no problem. I couldn’t find any warnings in the logs after generating the bitstream. (74.2 KB)


I downloaded that, opened it in Diamond, right clicked on ‘JEDEC’ in the ‘process’ tab, selected ‘rerun all’ and got the warnings again.
Then I uninstalled and re-installed Diamond and STILL got the warnings!
It does make a JEDEC file, though, and I’ve test it and it worked, so I might as well ignore the warnings!
PS: Are we using the same version of Diamond? Mine’s (First time I’ve seen a version with 5 numbers! I wonder what they all mean…)