How to easily sum two numbers in verilog?


#1

Hi, I’ve recently acquired a tinyFPGA Bx and after seeing everything working correctly, tried to do a 4 bit adder in verilog, but my code seems to have an error. I’ve looked everywhere for similar code, but they too did the same, without the error. The code is shown below and the error is:

“top.v:53: error: Cannot assign to array result. Did you forget a word index?”

and the line in question is in bold. Thanks in advance.

// look in pins.pcf for all the pin names on the TinyFPGA BX board
//`include “FullAdder.v”
module top (
input CLK, // 16MHz clock
input PIN_14,
input PIN_15,
input PIN_16,
input PIN_17,
input PIN_18,
input PIN_19,
input PIN_20,
input PIN_21,
output PIN_1,
output PIN_2,
output PIN_3,
output PIN_4,
output PIN_5,
output USBPU // USB pull-up resistor
);
// drive USB pull-up resistor to ‘0’ to disable USB
assign USBPU = 0;

////////
// Fazer uma implementação simples de uma ALU
////////

// sinais utilizados pela ALU

reg [25:0] counter;
reg result[4:0];
wire A[4:0];
wire B[4:0];

assign A[4] = 1'b0;
assign B[4] = 1'b0;
assign A[3] = PIN_14;
assign B[3] = PIN_18;
assign A[2] = PIN_15;
assign B[2] = PIN_19;
assign A[1] = PIN_16;
assign B[1] = PIN_20;
assign A[0] = PIN_17;
assign B[0] = PIN_21;

assign clock = counter[25];
// 26 bit counter used for the 'human perceivable' clock
always @(posedge CLK) begin
    counter <= counter + 1;
end
// sum implementation
always @(posedge clock) begin
    **result <= A+B;**
end // always

// light up the LED according to the pattern

assign PIN_1 = result[0];
assign PIN_2 = result[1];
assign PIN_3 = result[2];
assign PIN_4 = result[3];
assign PIN_5 = result[4];

endmodule


#2

reg [4:0] result;
wire [4:0] A;
wire [4:0] B;

not

reg result[4:0];
wire A[4:0];
wire B[4:0];


#3

Now it compiles! Thank you very much!