Hysteresis Issue (TinyFPGA A1)


Hey all,

I’m attempting to implement input hysteresis on my TinyFPGA A1 (MachXO2-256) as part of a debounce circuit, and I’ve been running tests using an Analog Discovery 2 to try and confirm that I’ve enabled hysteresis successfully using the FPGA datasheet and application notes from Lattice as a guide. I’m seeing some weird results in the output waveform that seem to indicate that either hysteresis isn’t actually enabled correctly, or I’ve made a mistake in my test setup/HDL (I’ve used Verilog before, but I’m still relatively inexperienced so I may have made a mistake that’s generating the weirdness I’m seeing).

First, here’s the superimposed input and output waveforms on the oscilloscope:
That’s an input sawtooth (blue) going from 0V to 3.3V at 100Hz, and an output (yellow) (image at 1V/div for both channels and 10ms/div). During the ramp, there’s a large voltage range over which toggling occurs. My understanding is that if hysteresis were being implemented as described in the sysIO Usage Guide (TN1202) I should be seeing 0V at the output until VIH is hit, at which point I should see 3.3V. I tested other waveforms (triangle, sine) and saw similar results at a variety of frequencies (1Hz - 10kHz) leading me to believe that something I’ve done is prohibiting hysteresis.

My HDL is identical to the TinyFPGA A1 template file except I’ve changed the input pin from “inout” to “input”, and changed the output pin from “inout” to “output”, and I’ve condensed the normal “assign” statements for both pins into a single assignment of the form: “assign out_pin = in_pin”. I’m not registering anything as the hysteresis should work with an asynchronous design, and including a register could lead to the appearance of hysteresis without it actually being enabled on the input depending on the relative frequencies of the clock and the test waveform. I can upload the .v file if needed, but the changes are limited to those four lines.

I changed the I/O configuration in the Lattice Diamond spreadsheet view. I set the input and output pins to “LVCMOS33” (these default to “LVCMOS25” for some reason), and changed hysteresis for the input pin to “LARGE”. I then confirmed that these changes were reflected in the .lpf file and everything looked good, so I synthesized and downloaded. When I saw the weirdness the first time, I tried enabling the bus keeper on the input pin as well (the datasheet gives the hysteresis voltage with both hysteresis and the bus keeper enabled, so I figured that might make a difference) and didn’t notice any change. I doubt it matters, but I also did the same test prior to trying to enable hysteresis in the first place to see if toggling occurred, as a point of comparison for my later tests while trying to enable hysteresis. I didn’t see any difference in any of those three experiments - I get toggling no matter what.

If anyone has any suggestions or can spot any mistake I’ve made, I’d greatly appreciate it. I know that debouncing can be done entirely in the HDL, but I’m deliberately trying to avoid that to familiarize myself more with the FPGA hardware. Right now I’m stumped as far as what’s wrong, so hopefully someone can point me in the right direction. Let me know if I can provide any other information to help pin down the issue.

Thanks in advance for the help!


I normally wouldn’t reply just to bump this thread, but I’ve tried reaching out to Lattice support about this issue, and they apparently won’t let you open a ticket with them unless you have a company email address (my .edu domain is excluded). I haven’t been able to find anything in their FAQs that shed any light on the problem, and since they’ve shut down their support forum I’m not sure where else to look. Even general suggestions would be appreciated, if you have any.