The hardware clock on the TinyFPGA BX is locked at 16MHz. This is essentially unchangeable, and is set by the oscillator circuitry.
That’s not quite the end of the story though. There’s a trick you can use internally in the FPGA to scale the clock. This is known as a PLL (Phase Locked Loop). A PLL allows you to take a clock at a certain frequency and scale it (either up or down).
The open source tools for the ICE40 come with a tool called icepll which can be used to generate the appropriate configuration for the PLL that comes built in to the ICE40 chips.
For example, if you wanted to generate a 50MHz clock for use inside the FPGA from the 16MHz external clock, you could use icepll to create a verilog module: