Initializing multiple BRAM modules


#1

Hi all,

Is there a clean way to initialize multiple BRAM modules with different values?

I’m working on a project where I need to instantiate 8 different BRAM modules, each initialized with different values (basically using the BRAM as ROMs). I have successfully instantiated the module below on the TinyFPGA BX. I could create 8 different modules that are the same except for the initialization values, but that seems wasteful and tedious…is there a better way?

Thanks for the tips :pray:

module BRAM(RESET, CLOCK, READ, ADDRESS, DOUT);
  input wire RESET;
  input wire CLOCK;
  input wire READ;
  input wire [10:0] ADDRESS;
  output reg [15:0] DOUT;


  reg [4:0] SYMCOUNT;
  reg [3:0] RE_R_c;
  wire [15:0] RDATA_R_c_0;

  always @(*) begin
    DOUT = RDATA_R_c_0;
  end

  always @(posedge CLOCK) begin
    if(RESET) begin
      RE_R_c <= 4'h0;
      SYMCOUNT <= 0;
    end
    else begin
      if(READ && !RE_R_c[0]) begin
        RE_R_c <= 4'hF;
        SYMCOUNT <= SYMCOUNT + 1'b1;
      end
      else if(SYMCOUNT==5'b11111) begin
        RE_R_c <= 4'h0;
        SYMCOUNT <= 0;
      end
      else if(RE_R_c[0]) begin
        SYMCOUNT <= SYMCOUNT + 1'b1;
      end
    end
  end
  /////////////////////////////////////////////
  //  Module instantiation
  /////////////////////////////////////////////
  //SB_RAM256x16
  SB_RAM40_4K ram256x16_inst_R0 ( 
   .RDATA(RDATA_R_c_0[15:0]),
   .RADDR({ADDRESS[10:4],(4'hF-ADDRESS[3:0])}),
   .RCLK(CLOCK),
   .RCLKE(RE_R_c[0]),
   .RE(RE_R_c[0]),
   .WADDR(11'd0),
   .WCLK(1'b0),
   .WCLKE(1'b0),
   .WDATA(16'd0),
   .WE(1'b0),
   .MASK(16'd0)
   );
   defparam ram256x16_inst_R0.READ_MODE=0; //256 x 16
   defparam ram256x16_inst_R0.WRITE_MODE=0;
   defparam ram256x16_inst_R0.INIT_0 =
   256'h08B5554924A4D524D6845555AA92895ED255A55556D6AD644FBD5694D6DB754B;
   defparam ram256x16_inst_R0.INIT_1 =
   256'h7695BB6D654D56FB48D6AD6B5554AD495ED2494AAD55488B6925652522955568;
   defparam ram256x16_inst_R0.INIT_2 =
   256'h104DB2254426A9255550157555A40ADDB524D64ADD55ED4555FF64AD55FF596B;
   defparam ram256x16_inst_R0.INIT_3 =
   256'h6D696FFAAB526FF6A92B7AABB526B24ADB75025AAAEA40A5554955412544DB20;
   defparam ram256x16_inst_R0.INIT_4 =
   256'h424AAD500B5115555292524F7508A55B6AAA4AED25DF52AAADDBB710DF7576B5;
   defparam ram256x16_inst_R0.INIT_5 =
   256'h6B576B6FB116EDDDA55557DA4DB525556DAA520AF748A51552AA915500AB5548;
   defparam ram256x16_inst_R0.INIT_6 =
   256'h9045BA442255216D225504B76B102B6AB7485755556FB48B6ADFEA4AAEFD56F5;
   defparam ram256x16_inst_R0.INIT_7 =
   256'h4DBB4EFDAA4AEFD5B644F7B5555B48576AB71026B768455095B10AA9084AF502;
   defparam ram256x16_inst_R0.INIT_8 =
   256'h42A912D54810DB515410D752A55550ADB2D7212B77B49572AF755B755557F72A;
   defparam ram256x16_inst_R0.INIT_9 =
   256'hB2ADFDA555BB55BDAAB549BBDB212B6AB72455A52AAB6409525B6408956A24B1;
   defparam ram256x16_inst_R0.INIT_A =
   256'h924A52AD50055AAB12249772257289556DAAA90AFF54B52D75B7557724BF775A;
   defparam ram256x16_inst_R0.INIT_B =
   256'h555BBF712DDAAB75B6AAA95DFA44AAB6D5548AB512DB49122AB5550057515291;
   defparam ram256x16_inst_R0.INIT_C =
   256'h92444DB10A4097B520856A4AD48AD48ADBB510DB5BDD22ADDB6ADF526D5AFFB2;
   defparam ram256x16_inst_R0.INIT_D =
   256'h496FFAAEB15BDAB6EDA90DF756D20AF6D5455A44DA8AB4811577208A216D5049;
   defparam ram256x16_inst_R0.INIT_E =
   256'hD408D54A908925DD009695555528AA916FD48A96DEDB509DF557BAB555B76FF2;
   defparam ram256x16_inst_R0.INIT_F =
   256'h12FEEDD55AB5BD95F748AD6F7554917F544D492AA5AA5540477545084AAAA902;
endmodule