Instantiating two PLLs with 16MHz clock


#1

I’m stuck on how to use both PLLs on the iCE40. From the documentation I’ve read I believe one needs to use the ‘SB_PLL40_2_PAD’ primitive so that the onboard 16MHz clock can be buffered and re-generated to drive the 2nd PLL. Can’t figure out how to get it to synthesize - I’ve been unable to find a way to route the 16MHz SB_IO to the “PACKAGEPIN” input on SB_PLL40_2_PAD.

Has anyone successfully generated two unique PLL outputs both driven by the onboard 16MHz clock?


#2

I’m not an expert, but I believe the TinyFPGA BX only has one PLL. Per here (https://tinyfpga.com/) it uses the ICE40LP8K. If we reference the datasheet here (http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf) we’ll see that it has 2 PLLs, but with a footnote “2. Only one PLL available on the 81 ucBGA package.”.

If we dig further on the TinyFPGA site, we can find the schematics here(https://github.com/tinyfpga/TinyFPGA-BX/blob/master/board/TinyFPGA-BX-Schematic.pdf) reference the iCE40-LP8K-CM81. Back to the datasheet again, in section 5-1, we’ll see that “CM81 = 81-Ball ucBGA (0.4 mm Pitch)”


#3

@jamon Egads, you’re right! Those darn footnotes. At least that explains it.

For any interested, I ended up using ‘SB_PLL40_2F_CORE’ which allows for two discrete clock outputs (same freq or half freq) that can both be globalized. The issue I was trying to solve was I had a fast clock for sampling something into RAM and a slow clock shoving it out a serial interface. Two domains so I could keep things speedy on the fast side. However, I was deriving the slow from the fast by using a counter to divide it down… which in itself was enough to slow down the design due to the adders in the always@. Having dual outputs on the PLL allows me to keep a tighter timing constraint on one of them and divide the other down further.