Is it possible to assign 16Mhz CLK to PIN_1 using TinyFPGA BX (and VHDL)


I am new to TinyFPGA, but have worked a little with FPGAs in the past, a few years ago.

I am using yosys and ghdl with the tinyfpga BX

The TingFPGA BX works perfectly with ghdl and yosys for basic cases, blink, etc…

However, when I try more advance cases, its not working as I’d expect, in this case Im trying to send a 16MHz clock out PIN_1.

Im not sure if
a ) it is not posible to assign 16Mhz CLK to PIN_1 with this fpga
b ) I have implemented the vhdl incorrectly / should be syncronous process
c ) tinyfpga and vhdl don’t work so nicely together / unsupported

Unfortunately I have been unable to get APIO and/or verilog working yet, to test using verilog…

Really appreciate any insight you could share, thank you.

Would you expect this to work on TinyFPGA? VHDL looks like this:
// all files saved to this github gist:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simple_clk_top IS
port (
CLK : in std_logic;
PIN_1 : out std_logic;
USBPU : out std_logic;
LED : out std_logic
end entity;

architecture Behavioral of simple_clk_top IS
PIN_1 <= CLK;
USBPU <= ‘0’;
LED <= ‘1’;
end Behavioral;


Hi Moolet, I can’t help you with your VHDL issues as I use Verilog, but I just went through setting up Atom/apio IDE so can help you with that. What happens when you try and use apio?


Hi Duncan,

thanks for your response, very much appreciated…

When I start Atom, I’m getting an error message which says “required APIO version >= 0.3.0<0.4”. I’m using apio version 0.5.4, perhaps I need to downgrade apio…

Im using Macos catalina.

I did manage to get icestudio working, I can build and upload “visual” verilog successfully now, which seems to be adequate for the moment. but even with Icestudio, Im still struggling to get a high speed clock signal out of the tinyfgpa. I managed to use the prescaler22 to output a slow clock, however when I assign PIN_1 <= CLK, it seems PIN_1 remains low… When I get a chance, Im going to try get apio working, and re-write my code in verilog.

Do you know if it is reasonable to expect a 16Mhz clk output from tinyfpga BX?

My goal is to synthesize a TDM audio output signal…

Thanks again, and kind regards,


Hi Nic,

Following the BX User Guide it has you install apio version 0.4.0b5 which is what I am using. It still gives the error message you indicated but it works for me (I’m using WIndows 10). Recommed you downgrade.

I have used the 16MHz clock in the BX as the source for a clock divider. The 16MHz clock is externally generated by a MEMS and hardwired to the pin called CLK, so this code will work to connect it to another pin (pin 14):

module top (
input CLK, // 16MHz clock
output PIN_14);
assign PIN_14 = CLK;

I tested this and it works :slight_smile:

General things I stumbled over while getting the flow working smoothly:

  1. I had multiple versions of Python installed, one of which would not uninstall and one of them was causing problems. I deleted all of them and did a clean install of Python 3.6 and that fixed my issue. Pretty sure Lattice tools use a different version of Python than apio requires so watch out of Python issues.
  2. Run “tinyprog --update-bootloader” as soon as you plug in your tiny board so the bootloader updates. Otherwise you will probably get an error about the board is not found.
  3. Set the appropriate COM port using “tinyprog -c COMxx” or again the board probably won’t be found.