I am new to TinyFPGA, but have worked a little with FPGAs in the past, a few years ago.
I am using yosys and ghdl with the tinyfpga BX
The TingFPGA BX works perfectly with ghdl and yosys for basic cases, blink, etc…
However, when I try more advance cases, its not working as I’d expect, in this case Im trying to send a 16MHz clock out PIN_1.
Im not sure if
a ) it is not posible to assign 16Mhz CLK to PIN_1 with this fpga
b ) I have implemented the vhdl incorrectly / should be syncronous process
c ) tinyfpga and vhdl don’t work so nicely together / unsupported
Unfortunately I have been unable to get APIO and/or verilog working yet, to test using verilog…
Really appreciate any insight you could share, thank you.
Would you expect this to work on TinyFPGA? VHDL looks like this:
// all files saved to this github gist: https://gist.github.com/newdigate/897481d3c70e83c7e2bd61e8b122c031#file-simple_clk_top-vhdl
entity simple_clk_top IS
CLK : in std_logic;
PIN_1 : out std_logic;
USBPU : out std_logic;
LED : out std_logic
architecture Behavioral of simple_clk_top IS
PIN_1 <= CLK;
USBPU <= ‘0’;
LED <= ‘1’;