LVDS input not appearing to have correct input characteristings. (AX2)


#1

Greetings experts!
I have a simple test running on an AX2 board. I take a ~40MHz input, sync a PLL to that input, and send a phase shifted version to the output.
So far, so good.

I have been using pin6 on the board (FPGA pin 21) as a single-ended input using the default LVCMOS25 input characteristics.

Next I want to set up board pins 6 and 5 as LVDS inputs, so that I can use a smaller input swing signal coming out of coax. (Assume I can deal with AC coupling and biassing the signal to the midpoint for both the true and complement inputs.)

What I am finding is that configuring the input to LVDS seems to be actually somewhat worse for my goal of syncing to a lower amplitude signal. I’m just doing this on solderless breadboard for now, so it could be a bit more noisy but, if I’m reading the spec sheet correctly, the threshold should be a swing of around 100mV. For me, it’s taking about a volt.

Any thoughts? Anyone here have experience of the differential inputs on this chip?

I’m including the .lpf file below, to show the input configuration.

Regards
Doug

BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP “pin1” SITE “13” ;
LOCATE COMP “pin2” SITE “14” ;
LOCATE COMP “pin3_sn” SITE “16” ;
LOCATE COMP “pin4_mosi” SITE “17” ;
LOCATE COMP “pin7_done” SITE “23” ;
LOCATE COMP “pin8_pgmn” SITE “25” ;
LOCATE COMP “pin9_jtgnb” SITE “26” ;
LOCATE COMP “pin10_sda” SITE “27” ;
LOCATE COMP “pin11_scl” SITE “28” ;
LOCATE COMP “pin16” SITE “4” ;
LOCATE COMP “pin17” SITE “5” ;
LOCATE COMP “pin18_cs” SITE “8” ;
LOCATE COMP “pin19_sclk” SITE “9” ;
LOCATE COMP “pin20_miso” SITE “10” ;
LOCATE COMP “pin21” SITE “11” ;
LOCATE COMP “pin22” SITE “12” ;
IOBUF PORT “pin6” IO_TYPE=LVDS25 ;
IOBUF PORT “pin5” PULLMODE=NONE IO_TYPE=MLVDS25E ;
LOCATE COMP “pin6” SITE “21” ;