MACHX02-256- 48 PIN QFN JTAG Pin Numbers


#1

I’m struggling with Lattice documentation. What I am unable to find is the jtag interface pin numbers.

Where in the lattice documents are they defined for the various packages?

Pin 41 is jtag enable… that was discovered when adding
SYSCONFIG JTAG_PORT=DISABLE MUX_CONFIGURATION_PORTS=ENABLE;
to the .lpf file which was learned when designing the tinyfpga A1.

Once added Pins 44, 45, 47, 48 then appeared in the VREF assignmnet list and pin 41 was removed. These must be the JTAG pins. But where in the lattice documents are they defined for the various packages?

The documentation leaves so much to be desired!


#2

After looking at the CREATE VREF in spreadsheet view I figure out this file contained the information.

MachXO248-PinQFNPackageMigrationFile.csv

found here

https://www.latticesemi.com/Products/FPGAandCPLD/MachXO2

So now the pin numbers are figured out.


#3