Min/max possible generated PLL clock for BX?


#1

Given the input frequency is 16 MHz, what’s the minimum and maximum clocks one can generate internally via the PLL? Seems like one may be able to go below 16 MHz via iCEcube2 (but icepll won’t tolerate this), and up to 275 MHz.

Is it really capable of 275 MHz? The performance summary for any frequency above 16 MHz is a bit confusing (for 50MHz the “estimated frequency” is just over 100 MHz), and while I’m trying a very simple design out (basically the blinker demo) I wonder exactly what I should be taking away from that summary.

                                    Requested     Estimated     Requested     Estimated                 Clock                        Clock           
Starting Clock                      Frequency     Frequency     Period        Period        Slack       Type                         Group           
-----------------------------------------------------------------------------------------------------------------------------------------------------
CLK_16mhz                           16.0 MHz      NA            62.500        NA            DCM/PLL     declared                     default_clkgroup
my_pll|PLLOUTCORE_derived_clock     50.0 MHz      100.8 MHz     20.000        9.922         10.078      derived (from CLK_16mhz)     default_clkgroup
=====================================================================================================================================================