Noob needs help


Hi I’m following the guide at

I don’t know verilog or vhdl, so I’m not sure where to copy and paste the example code onto the template.

Could someone update the guide or at least post the correct code? Thanks!!



I believe that the code is supposed to be pasted just before the “endmodule” at the end.

Here’s the A1 version after following the instructions. Unfortunately I don’t have an A1, so can’t verify this on an actual device.

module TinyFPGA_A1 (
  inout pin1,
  inout pin2,
  inout pin3_sn,
  inout pin4_mosi,
  inout pin5,
  inout pin6,
  inout pin7_done,
  inout pin8_pgmn,
  inout pin9_jtgnb,
  inout pin10_sda,
  inout pin11_scl,
  //inout pin12_tdo,
  //inout pin13_tdi,
  //inout pin14_tck,
  //inout pin15_tms,
  inout pin16,
  inout pin17,
  inout pin18_cs,
  inout pin19_sclk,
  inout pin20_miso,
  inout pin21,
  inout pin22

  // left side of board
  assign pin1 = 1'bz;
  assign pin2 = 1'bz;
  assign pin3_sn = 1'bz;
  assign pin4_mosi = 1'bz;
  assign pin5 = 1'bz;
  assign pin6 = 1'bz;
  assign pin7_done = 1'bz;
  assign pin8_pgmn = 1'bz;
  assign pin9_jtgnb = led_timer[23];
  assign pin10_sda = led_timer[22];
  assign pin11_scl = led_timer[21];
  // right side of board
  //assign pin12_tdo = 1'bz;
  //assign pin13_tdi = 1'bz;
  //assign pin14_tck = 1'bz;
  //assign pin15_tms = 1'bz;
  assign pin16 = 1'bz;
  assign pin17 = 1'bz;
  assign pin18_cs = 1'bz;
  assign pin19_sclk = 1'bz;
  assign pin20_miso = 1'bz;
  assign pin21 = 1'bz;
  assign pin22 = 1'bz;

  wire clk;
  OSCH #(
  ) internal_oscillator_inst (

  reg [23:0] led_timer;
  always @(posedge clk) begin
    led_timer <= led_timer + 1; 


A little bit more background about what’s going on:

The top-level module defines all of the pins available on the TinyFPGA. You can allocate them to whatever you want.

There are a bunch of “assign” statements that set most of the pins to a high impedance (z) state. The 1'b prefix simply means “1-bit-binary-value”.

After you’ve worked through the tutorial pins 9,10 and 11 are assigned the values of bits 23, 22, and 21 of the led_timer register respectively.

The always block at the bottom increments led_timer once per rising edge of the clk signal. ie. at 2.08MHz. This means that in 1 second, led_timer has counted to just over 2 million.

Sorry if this is getting too n00b for you, but it also means that individual bits of led_timer will cycle at 2080000 / (2^b) Hz (where b is the number of the bit). So bit 23 cycles at about 0.25Hz, bit 22 at 0.5Hz, bit 21 at 1Hz.

Hope that helps. Good luck!


Cool that did it!

Now I can really start learning! :slight_smile:


(Joined the forum so I could post this) Hello! I do not understand how Luke came about this part:

  ) internal_oscillator_inst (

I don’t recgognize it as Verilog syntax nor is this block of code from the MachX02 clock usage guide either. That usage guide explains the .STDBY and .OSC settings, although not the .NOM_FREQ syntax. Is this syntax some kind of preprocessor directive or a macro or something? Is it assembly in Verilog to allow control of this specific chip’s hardware beyond using normal Verilog syntax?


It looks like standard verilog to me. It’s instantiating the module OSCH, with a parameter NOM_FREQ , and ports STBY and OSC…


Ok thank you. I just need to learn more Verilog then!


No problems, :slight_smile: I’m new to this myself so 6 months ago it all looked like gibberish to me too.

Parameterized modules are quite a powerful way of making your verilog configurable/reusable…


@gundy Just in case it helps someone, you can find those instantiation templates in the iCE40 datasheet. Those are modules physically present in the device, thus no HDL code has to be written appart from this snippet. Those tiny FPGAs don’t contain much hard cores so you don’t get too lost as a beginner, but other fpgas contain much more