I tried using the HDL generation wizard to make a 96MHz clock and got this:
Which dutifully reports in the comments that it is a x6 PLL, (16MHz in, 96MHz out). But in reality, it creates a 192MHz clock (!) and this is consistent with the formulae in the app notes if one looks. I’ve fixed this by making OUTQ one bigger but is this something people have encountered?
I haven’t had this same problem with the icecube2 PLL parameter generator, but I wasn’t a big fan of the automatically generated file. I found it was easy enough to set the PLL parameters myself according to the rules in the datasheet.