I am having troubles simulating my code now that i have added a ppl to generate the internal clock.
I am using apio sim, and it looks like that all the PLL outputs are Hiz (PLLOUTCORE included).
The code is running perfectly on the FPGA itself and I can see the PLL working as I have tested with different clock speeds.
Is there any magic trick I need to do on the test bench to enable pll simulation?
here my PLL code:
localparam PLL_DIVF_40MHz = 7’b0100111;
// CLOCK PLL
) pll_inst (