Pll not simulating properly with apio


#1

Hi There,

I am having troubles simulating my code now that i have added a ppl to generate the internal clock.
I am using apio sim, and it looks like that all the PLL outputs are Hiz (PLLOUTCORE included).
The code is running perfectly on the FPGA itself and I can see the PLL working as I have tested with different clock speeds.
Is there any magic trick I need to do on the test bench to enable pll simulation?

Thanks!!!

here my PLL code:

localparam PLL_DIVF_40MHz = 7’b0100111;
// CLOCK PLL
SB_PLL40_CORE #(
.DIVR(4’b0000),
.DIVF(PLL_DIVF_40MHz),
.DIVQ(3’b100),
.FILTER_RANGE(3’b001),
.FEEDBACK_PATH(“SIMPLE”),
.DELAY_ADJUSTMENT_MODE_FEEDBACK(“FIXED”),
.FDA_FEEDBACK(4’b0000),
.DELAY_ADJUSTMENT_MODE_RELATIVE(“FIXED”),
.FDA_RELATIVE(4’b0000),
.SHIFTREG_DIV_MODE(2’b00),
.PLLOUT_SELECT(“GENCLK”),
.ENABLE_ICEGATE(1’b0)
) pll_inst (
.REFERENCECLK(CLK_PIN),
.PLLOUTCORE(CLK),
.PLLOUTGLOBAL(),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(1’b1),
.BYPASS(1’b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK()
);


#2

There is no open source simulation model with the PLL. I think iCEcube might include a sim model of some sorts, but I don’t know whether or not it would work in Icarus (and it may well slow down the simulation substantially).

In general, the best approach would be to use something like `ifdef SIM to replace the PLL instantiation with a simple clock generator in simulation.