Pll not simulating properly with apio


Hi There,

I am having troubles simulating my code now that i have added a ppl to generate the internal clock.
I am using apio sim, and it looks like that all the PLL outputs are Hiz (PLLOUTCORE included).
The code is running perfectly on the FPGA itself and I can see the PLL working as I have tested with different clock speeds.
Is there any magic trick I need to do on the test bench to enable pll simulation?


here my PLL code:

localparam PLL_DIVF_40MHz = 7’b0100111;
) pll_inst (


There is no open source simulation model with the PLL. I think iCEcube might include a sim model of some sorts, but I don’t know whether or not it would work in Icarus (and it may well slow down the simulation substantially).

In general, the best approach would be to use something like `ifdef SIM to replace the PLL instantiation with a simple clock generator in simulation.