Resolved - Lattice Diamond - Error with .ldc constraint, frustration growing


The design has an internal oscillator of 2.08 mhz. The 2.08 logic has no timing errors reported once compiled, place and routed. An async clock input, 100 MHz rate, has timing errors. Trying to use the constraints to set the clock rate. I cannot seem to properly identify the net, pin, or port to set the constraint. It failed with the below warnings.

constraint.lcd file line is: create_clock -period 50.000000 -name clk1 [get_nets pin22_c]

--------------------------it failed using the constraint with this message -----------------------------------------
WARNING - No object with type NET found matching pin22_c;
WARNING - Ignoring Constraint: create_clock -period 50.000000 -name clk1 [get_nets pin22_c].

------------------------the report before using the constrain file ----------------------------------------------
Constraint: create_clock -period 5.000000 -name clk1 [get_nets pin22_c]
119 items scored, 21 timing errors detected.

Error: The following path violates requirements by 2.088ns
Logical Details: Cell type Pin type Cell name (clock net +/-)

Source: FD1P3IX CK \so/sireaddone_30 (from pin22_c +)
Destination: FD1S3AX D \so/shiftreg_i4 (to pin22_c +)

Delay: 6.928ns (27.8% logic, 72.2% route), 4 logic levels.
Constraint Details:

  6.928ns data_path \so/sireaddone_30 to \so/shiftreg_i4 violates
  5.000ns delay constraint less
  0.160ns L_S requirement (totaling 4.840ns) by 2.088ns


All day struggle with lattice diamond trying to set the clock constraint… finally figured out what needs doing.

process the design so to have a netlist

i used an empty constraint abc.lcd file so it was in the file list

right click on this file list tab and open with lcd editor

now double click the source box and selected clock port, select pin22

double click the other boxes and enter desired values

then under file click the save to save the file

rerun the process and all is well and that clock is set 20 MHz

be happy, but dissapointed with LATTICE!

then look at the file to find the syntax is not even close to what the manuals state!

create_clock -period 50.000000 -name asyncclk [ get_ports { pin22 } ]