The Error has been resolved - needed to edit the template_a1.lpf file and comment out //LOCATE COMP “pin9_jtgnb” SITE “26” ;
Is there any decent documentation to better go through the basics? OMG surely this would kill interest in many amateurs attempting to use lattice FPGAs
Lattice Synthesis Engine results
WARNING - I/O Port pin9_jtgnb 's net has no driver and is unused.
ERROR - The state of the assigned pin  conflicts with the config mode and cannot be assigned to the port [pin9_jtgnb]
How is the pin9_jtgnb in the verilog file handled. Also is there something else that needs to be setup in the lattice environment.
in the verilog file
// JTAG_PORT in spreadsheet view has been disabled
// now the jtag pins can be used as i/o
// connect pin9_jtgnb to pulldown
inout pin9_jtgnb, // JTAGENB