Resolved - TinyFPGA A1 Beginner, verilog warnings and other basic questions


#1

Managed to worked through why warnings were in the basic file and resolved all and solved errors caused as result.

Changed up the design some to add an output, reset input, reset register,and changed the led output pins. Changing the LED output pin pin9_jtgnb is required as mentioned in the next paragraph. So I moved them all to pins 5, 6, & 7.

Also figured out how to use the programming pins after the chip is programmed. Remove pin9_jtgnb from the template_a1.lpf


module TinyFPGA_A1 (
output pin1, // PLL CLK T2_1 FPGA PIN 13
inout pin2, // PLL CLK C2_1 FPGA PIN 14
inout pin3_sn, // SLAVE CS FPGA PIN 16
inout pin4_mosi, // MOSI FPGA PIN 17
output pin5, // PLL CLK C1_0 FPGA PIN 20
output pin6, // PLL CLK T1_0 FPGA PIN 21
output pin7_done, // DONE FPGA PIN 23
inout pin8_pgmn, // PROGRAMN FPGA PIN 25

// JTAG_PORT in Latice Diamond spreadsheet view has been DISABLED
// now the jtag pins can be used as i/o
// connect pin9_jtgnb to ground using internal pulldown
//
// EDIT template_a1.lpf file and comment out pin9_jtgnb pin!!!
//
//inout pin9_jtgnb, // JTAGENB FPGA PIN 26 weak pulldown

inout pin10_sda, // SDA, PLL CLK C0_0 FPGA PIN 27
inout pin11_scl, // SCL, PLL CLK T0_0 FPGA PIN 28
inout pin12_tdo, // PGRM INTF TDO FPGA PIN 1
inout pin13_tdi, // PGRM INTF TDI FPGA PIN 32
inout pin14_tck, // PGRM INTF TCK FPGA PIN 30
inout pin15_tms, // PGRM INTF TMS FPGA PIN 29
inout pin16, // PLL CLK T3_0 FPGA PIN 4
inout pin17, // PLL CLK C3_0 FPGA PIN 5
inout pin18_cs, // SPI MASTER CS FPGA PIN 8
inout pin19_sclk, // SPI CLK FPGA PIN 9
inout pin20_miso, // SPI MISO FPGA PIN 10
output pin21, // PLL CLK T2_0 FPGA PIN 11
inout pin22 // PLL CLK C2_0 FPGA PIN 12
);

// left side of board
assign pin1 = 1’bz;
assign pin2 = 1’bz;
assign pin3_sn = 1’bz;
assign pin4_mosi = 1’bz;
assign pin5 = 1’bz;
assign pin6 = 1’bz;
assign pin7_done = 1’bz;
assign pin8_pgmn = 1’bz;
assign pin10_sda = 1’bz;
assign pin11_scl = 1’bz;

// right side of board

// programmer interface
assign pin12_tdo = 1’bz;
assign pin13_tdi = 1’bz;
assign pin14_tck = 1’bz;
assign pin15_tms = 1’bz;

assign pin16 = 1’bz;
assign pin17 = 1’bz;
assign pin18_cs = 1’bz;
assign pin19_sclk = 1’bz;
assign pin20_miso = 1’bz;
assign pin21 = pin22;
assign pin22 = 1’bz;

wire clk;
wire oscstdby;

OSCH #(
.NOM_FREQ(“2.08”)
) internal_oscillator_inst (
.STDBY(1’b0),
.OSC(clk),
.SEDSTDBY(oscstdby)
);

wire reset = pin22;
reg reset_reg;

always @(posedge clk) begin
reset_reg = reset;
end

assign pin1 = pin22;

reg [23:0] led_timer;

always @(posedge clk) begin
if (reset_reg)
led_timer <= 24’d0;
else
led_timer <= led_timer + 1’b1;
end

assign pin5 = led_timer[23];
assign pin6 = led_timer[22];
assign pin7_done = led_timer[21];

endmodule


A2 Programming Issue Using Tiny Programmer