Seeing how Lattice Diamond implements an expression


Is there a way of seeing how Lattice Diamond implements an expression?
My (as yet untested) VGA pattern generator Verilog source code has an expression “CounterY<10’d480”. With my programmer hat on, the ‘obvious’ way to implement that is with a 10-bit adder (CounterY+(10’d-480)) and seeing if there’s a carry. But, since
10’d480=10’b0111100000 and I know that CounterY never exceeds 10’d524=10’b1000001100,
if I were doing this with 74xx-series chips I’d implement it as
(CounterY[9]==1’b0) && (Counter[8:5]!=4’b1111)
So I’m wondering if the latter expression would take up less space in the FPGA than the former. (It fits anyway, so I’m only asking in anticipation of some future time when I’ll want to squeeze as much as possible into my A1.)


So you should be able to see the RTL synthesis which will show you exactly what gates are being used. By default I believe a 10 bit comparator will be used since the tool doesnt know if you are counting by 1 or 10 or 200. Therefore, I believe the second option is better. It provides more information to the sythesis tool and should use less of the FPGA.


Thanks, Samuel.

So you should be able to see the RTL synthesis

How do I see that? I know very little about FPGAs or Diamond!

Idle curiosity: is there any way in Verilog that I could specify that an n-bit register won’t hold all possible 2**n values (like integer subranges in Pascal and Ada)?


I dont use lattice diamond, sorry. You can make a finite state machine that will optimize away the unused parts of the lut, but I feel that is not what you are going for.