Simulate reg arrays. How?


Hi there.
I am trying to use reg arrays in VERILOG (apio) and would like to simulate but they are not shown in the available routes.
f.e. reg [0:7] MEM_TEST [0:5]; does not show up in the list.
but if I get rid of the array and declare only a singel register
reg [0:7] MEM_TEST;
this is shown in the list of simulated routes.
What do I wrong? Is it possible to simulate an array behavior?
Regards and thanx in advance, Harald.


Arrays aren’t dumped to the VCD file by default. In Icarus Verilog you need to use a for loop to dump elements individually - see