I’ve been getting started with the A series boards, and I came across an issue a while back that I’ve been unable to resolve.
Fundamentally, I’m trying to chain two clock divider modules that I wrote, and I’m getting weird artefacts from the second in the chain.
screenshot removed due to 1-image limit (see comment for filename)
I intended to run the
OSCH clock at ~2 MHz, into
clkdiv1 (a divide by 8… 4 × 2), and then into
clkdiv2 (again, divide by 8).
Instead, I’m seeing something come out of
clkdiv2 (~1 MHz) around where I’d expect to see its transitions.
I’ve tried adding a global reset, with no luck:
I decided to backtrack and have found another approach that works for my current project, but I’d still really like to understand what’s going on here…
Example projects with bitstreams are here:
Any advice would be greatly appreciated.