Structure of Verilog Project - Beginner


Hello Everyone,

I’m new to FPGAs and have some questions about how to make a simple project. I’ve run the blink_project that is mentioned in the tutorial and I see that it only has one .v file called top.v. This implements the top level module which makes sense.

However, when I look at Verilog tutorials such as this one: I get confused about how the files in my project should be structured. Should the music module from this tutorial go in its own file (music.v) or can I put it in the top.v file too? Does each module have to go in a file that has the same name as the module?

Also, do you always have to have a top.v file and a top module (kind of like main() in C)?

Thanks so much for your help! I feel this is a very basic question, but I haven’t been able to find an answer on any tutorials.



You can do either of those.

No, it doesn’t have to.

No, in general yosys will deduce the top level module, or there is a a parameter to yosys to allow you to specify the name of the top level module, although I cannot remember how apio and the atom plugin deals with that. Where you can, sticking to the convention of having a top.v is not a bad idea.

I have implemented most of those fpga4fun projects on ice40 boards, but not all of them on the TinyFPGA BX. Here is a TinyFPGA BX project that is similar to the fpga4fun music projects -


Thanks so much Lawrie! The TinyFPGA BX implementations of these projects are really helpful.