Hi all! Getting my new TinyFPGA Bx is really exciting, and I can’t wait to use it! However, this is not my first time using FPGAs. When I was taught in school, we did most of our HDL coding in SystemVerilog. Are there any tools currently that allow me to design in SystemVerilog for the ICE40LP8k-CM81 in SystemVerilog instead of strictly Verilog/VHDL? If so, are there any good tutorials or documentation I can read to get started? Thanks in advance!
So after a bit of head scratching and looking around for the right tools, it would appear that the IceStorm flow is the perfect tool-chain to use SystemVerilog on the TinyFPGA. I used yosys for synthesis and generating a netlist, and then I used nextpnr to place and route, and generate the ASCII file. Finally, I used icepack to convert the asc file to a bin. This allowed me then to use tinyprog -p .bin to program it onto my TinyFPGA Bx.
For anyone who needs some further pointers, the following links helped tremendously:
Especially the README for nextpnr and the example they give.