Testbench issue


#1

HI there!
If I use the apio simulate I get only part of the declared wires. Is there a way to tell the testbench which wires to show in the diagram? Seems to me that some are missing and some not.
Regards; Harald

// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
input CLK, // 16MHz clock
input PIN_21, // /CS of TinyFPGA SPI
output PIN_22, // MISO
input PIN_23, // MOSI
input PIN_24, // SPI clock

output  LED,     // User/boot LED next to power LED
output  USBPU   // USB pull-up resistor

);
// drive USB pull-up resistor to ‘0’ to disable USB
assign USBPU = 0;
wire SCK,SS,MOSI, MISO;
wire led;
wire RX_BYTE_AVAILABLE;
wire TX_BYTE_READY_TO_WRITE;
wire TRANSACTION_BEGIN;
wire [0:7] RX_BYTE;
reg [0:7] TX_BYTE = 8’h22;
wire [2:0] BYTE_CNT;
reg [0:7] MEM_TEST[0:5];
spi_slave Slave(.clk(CLK), .sclk(PIN_24),.miso(PIN_22),.mosi(PIN_23),.ss(PIN_21),.rx_byte_available(RX_BYTE_AVAILABLE),
.rx_byte(RX_BYTE),.tx_byte_ready_to_write(TX_BYTE_READY_TO_WRITE),.tx_byte(TX_BYTE),.transaction_begin(TRANSACTION_BEGIN),.byte_cnt(BYTE_CNT));

always @(posedge CLK) begin
  MEM_TEST[0] <= 8'h10;
  MEM_TEST[1] <= 8'h21;
  MEM_TEST[2] <= 8'h32;
  MEM_TEST[3] <= 8'h43;
  MEM_TEST[4] <= 8'h54;
  MEM_TEST[5] <= 8'h65;
end

always @(posedge TX_BYTE_READY_TO_WRITE) begin
  TX_BYTE <= MEM_TEST[RX_BYTE - 8'h88 + 8'h03];
end

endmodule