TinyFPGA based on iCE40-UP5K-SG48



I have been following the TinyFPGA project for a while now and own a BX board. I also have listened to the AMP hour podcast (on the production of the boards and such) and got motivated to try and design a board similar to the TinyFPGA BX design (with the same bootloader).

I plan to use the iCE40-UP5K-SG48 ICE40(non BGA) FPGA but hope to clone the rest of the design based on TinyFPGA.

I wanted to thank @lukevalenty for inspiring me !


Awesome! Keep us posted. :slight_smile:


I Have been doing the basic research and very much would like to still get rid of the Cristal oscillator to have a few components less to put on the board/lower the cost but this is probably now the way to go for version 0.1.



I have a few questions about the BX schematics. It would help me better understand some part of the design.

Q1) Why is clock going not a normal pin e.g. IOL_2B and not a Gobal BIN pin?)
Q2) Why is SPI SI (Slave in) connected to IOB_105_SDO AND IOB_104_CBSEL1?
Q3) A few pins look… randomly attached to either ground of 3v3. Is this to satify boot requirements (e.g. ensure the device boots into SPI master mode) ? (IOT_188 in this case)
Q4) Some other pins are corrected to +1v2. Is this for the same reason? Do not all the banks operate at 3v3?
Q5) is VCCPLL (I don’t have this on the ice40up5k) is powered via a 100 Ohm resistor and if so why?

Thank you


Summary for most of the questions: Routing signals to pads on the 0.4mm pitch BGA package was very tricky. Current PCB design does not use advanced techniques like microvias. These places large restrictions on how the FPGA is laid out.

  1. I think I could move this to a global buffer pin in a future revision. This was an oversight on my part.
  2. This pad is a few layers inside the footprint, it had to be routed out by going through another pad.
  3. Some power and ground pads had to be routed over other pads.
  4. Same as 3.
  5. The 100 ohm resistor and capacitors connected to VCCPLL form a simple filter to filter the PLL power supply. The PLL is sensitive to voltage level and excessive noise can cause instability on the PLL output.

Here’s a quick picture of the footprint that may help you understand some of the strangeness in the schematic:


I am not an experienced developer of circuit boad or anything but at the first glance I recognized design intention of TinyFPGA BX’s PCB. Those patterns around the BGA package. I’m deeply impressed and excited being realized that this sort of hobbist oriented design is actually possible.
Luke, thank you very much for sharing your knowledge with us!

I want to try if I can push it farther and make it work on just an ordinary two layer PCB.


Hi, just q quick update. I replaced the FPGA by ICE40-UP5K and generated my first netlist and imported into the PCB design.

After removing the traces it looks like this:

I don’t know how many layers I will need but it does not to to complex at this point.


I tried a little bit to do the layout and moved the capacitors/resistors to the bottom layer. I also randomly replaced a few components (to not have warning in kicad about unkown footprints) I will soon have to decide what components to use.


Some warnings, before you waste your time:

  • The UP5k also needs a 100 Ohm with a capacitor for filtering the PLL.
  • There are already similar boards around: The IceBreaker Mini and the Upduino 2, maybe some more. The Upduino is very cheap.
  • Lukes old bootloader did not work on the UltraPlus, the FPGAs are too slow, I fear also the new may not work if it still needs 48 MHz clock.


I’m working on a new bootloader that works on the UP5K. It has no problem meeting 48 MHz…in fact the USB front end could be clocked at more than twice that!



Thanks for the information. I kept the 100 Ohm resistor. I also already ordered a Upduino (did not arrive yet) thank you.

For Future reference there is a list of document here https://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx#_0FE55F18073946BB968FC580D328F191 and one of them is https://www.latticesemi.com/view_document?document_id=47779 (the checklist that among other things talks about the 100 Ohm resistor)


Thanks sounds great. is the bootloader based on TinyFPGA-Bootloader?



Today I “finished” the design. The result is a two layer pcb. I had to remove a few lines (the SPI WP and SPI HOLD) but besides that I think this all might work.

What next?

I would very much like some help in reviewing the PCB schematics (that can be found here)
I used plot -> pdf to make the pdf searchable.

I will probably need to redo the layout (at least once) when I have all the components and to clean up a little


I changed the name of the project (to no confuse people) and today ordered the first PCBs from oshpark.

During the review I “discovered” that the there should be a pull-up on the CDONE lines but this is also not present in the TinyFPGA-BX. I hope I did not make to many mistakes.


And today a bunch of parts arrived including the ICE40-UP5K-SG48.

so… Money spent and boards ordered from oshpark. It is becoming an expensive hobby


I am still waiting for the perfect purple boards from oshpark. Living in The Netherlands this might not have been the best choice (in terms of delivery speed)


We are nearing the moment of truth.

The boards arrived from oshpark!



yesterday I assembled the first board and this morning validated voltages and clock and this morning I powered the device!

3v3 is present, and so does 1v2 and I also validated that the clock was working. The main problem currently is that I ordered the wrong SPI chip and that is does not fit on the footprint.


Still waiting for my parts to come:(. I started on a test jig to be able to program the device)


Just stumbled over this post. I also started to layout a clone with a iCE40-UP5K-SG48 chip a few months back. The main reason was to learn KiCad and my interest in using the DSP slices on the chip. Not yet sure if i am able to solder the pcb by hand nor it will work.

The KiCad project files are available under https://github.com/glanzi/TinyFPGA-UP on GitHub.

Thank you @lukevalenty for your great TinyFPGA project!