TinyFPGA EX Preview


#1

I’m working on expanding the TinyFPGA line-up with an additional series with new features. This is a significantly more complicated and capable board than the A- and B-series boards. It will be available sometime in the first half of 2018.

The heart of the TinyFPGA EX boards is the ECP5 FPGA from Lattice. I’ll release more details as prototypes come back and specifications start firming up.

Until then, here’s a render of the board in its current form:


#2

Is that an SD card slot!?


#3

Current specs:

  • Micro SD Card Slot (fully connected to all SD card interface signals)
  • 8 Megabytes HyperRAM (low pin count DDR)
  • ECP5 FPGA with 12k, 25k, or 45k LUTs
  • 8 Megabytes SPI Flash
  • 3.3v switching power supply for IOs
    • 2.5v LDO for FPGA aux rail
    • 1.8v LDO for HyperRAM and associated FPGA IOs
  • 1.1v switching power supply for FPGA vcore (up to 3 amps…)
  • 16MHz MEMS clock
  • Micro USB connector
  • 42 GPIOs (not shared with SPI, JTAG, or any other special pin)
  • JTAG, SPI, USB configuration interface test pads on bottom

#4

I posted the project to hackaday.io: https://hackaday.io/project/28266-tinyfpga-e-series

I’ll be updating the hackaday.io project page as new progress is made.


#5

Cool. I could use a small board with a 1.8V regulator to implement a 1.8V MIPI RFFE protocol without level translators. If VDD to the GPIO banks was connected thru a 0 ohm resistor, it would be nearly perfect because it would be very easy to route the 1.8V over. Will this have a PLL to run the core at some multiple of 16MHz?


#6

It will have up to 4 PLLs, so you will have a lot of options for clocks. The 16MHz clock source is not set in stone, I have some flexibility in the clock frequency I pick. The prototype boards I ordered for manufacture will have 16MHz clocks on them.

I think I would have to change the board too much in order to support 1.8v GPIOs. I’ll take a look at it, but no promises. I already ordered prototypes and they were so darn expensive.

On the other hand…this isn’t the last board I’ll be making with the ECP5 FPGA. I’m planning a larger board that may have programmable voltage regulators for the IO banks. This would let you change GPIO voltages dynamically. That future board will be something like 4" x 4".


#7

Do you and/or have you developed the interface code for Hyperbus? (HyperRam / Flash). Work with the lattice fpga’s quite a lot and am extremely interested in seeing an opensource version of the Hyperbus interface.

Regards.


#8

I haven’t yet worked on the HyperRAM or HyperBus interface. Once I am able to get the TinyFPGA EX crowd funding campaign going I’ll be developing an open source controller or leveraging an existing one. I know that Kevin Hubbard wants to make one and Greg Davill is working on one. https://twitter.com/gregdavill/status/986956102548910081?s=21


#9

Were you Targeting 100 Mhz or 133 Mhz parts on your board? I’m all for releasing an Open Source version of a HyperBus controller (Ram and Flash); Was just poking around to see if someone had already released one. Seen some work that would likely support HyperBus even on the ICE FPGA’s (albeit at a slower data rate perhaps).

Will see what I can get going here over the next week or so with my poking around at it.

Regards,

Jonathan Smith


#10

The EX has a 133MHz part on it. Would be great to get that speed but we will see. If you make an open core, see if you can abstract the lowest layer so that DDR IOs from different FPGA families will be able to be plugged in.


#11

Agreed, as well as some, hopefully, framework for handling bursting if not multiple outstanding transactions… We shall see…


#12

Maybe use a standard interface at the top like Wishbone b4 that supports bursting. Then it will be easier for others to use and maybe we can reuse an open source cache core on top.


#13

@Beowulfdance, here’s a HyperRAM interface just released by Kevin Hubbard from Black Mesa Labs: https://github.com/blackmesalabs/hyperram


#14

It has been a while, are there any updates???
I’m eagar to get my hands on one of these!!!


#15

The design has been updated significantly…I added a USB type-C connector as well as options for a 5gbit SERDES.


#16

Very cool!
Any idea when this will get released?
Where would SerDes connect? Are you planning on transfering data over USB-C?
I think Lattice has free tools but you have to pay for the version that supports SerDes and get a licence for the IP to use it, is that right?

Thanks - mark


#17

Any further updates on TinyFPGA EX?


#18

I was wondering if the EX board will also come in a castellated variant for surface mounting. I am planning on a simple game console along the lines of what Fabien is doing with the BX.

Thanks.


#19

Any updates on the status of TinyFPGA EX???