TinyFPGA with Logisim Evolution?


#1

Hello!

I have never messed around with a FPGA before, but i have recently finished a 8 bit Logisim CPU that i would like to get running on one if possible.

The problem i have here is that i do not know if i could use this with Logisim Evolution (i do plan to try learning Verilog and VHDL later, but for now i just want to export the designs I’ve made automatically)…

In Logi Evo, since the fpga board isn’t in the list it’s requesting a board description file, however i cannot find one online, and I’m not sure how to create one (i tried throwing random files (one being XML since it seemed to like those) into the board editor, but that didn’t let me do anything).

(I’m assuming it’s a schematic of the board for it to design the Verilog code based off of?)


#2

I was able to find logisim’s requirements for the image, and how to create the XML on the french wiki entry.

https://github.com/reds-heig/logisim-evolution/wiki/Adding-a-new-board - Got to use google translator


#3

I used to use the original Logisim and was disappointed with where it was left off. Thank you for letting me know about Logisim-Evolution! I will be following this thread hoping to see a TinyFPGA BX board added to the known boards!


#4

There’s actually many different forks of the original, even some specialized forks of Logisim-Evolution made for specific FPGAs. I know a couple of people who use a few different versions at once for a particular project they are working on. If i can finish my template and get everything working for myself I’ll see about posting the files so others can just drag and drop. I’m just waiting on some components and the TinyFPGA breakout board i ordered from Tall Dog on tindie so i can hookup my CPU design to a display and inputs, and test if Evo’s export works for the board.


#5

Heres a few of the forks:

https://code.google.com/archive/p/logisim-iitd/

https://www.cs.cornell.edu/courses/cs3410/2015sp/\

(written from scratch and includes FPGA/verilog export support using GHDL) https://github.com/hneemann/Digital


#6

https://github.com/hneemann/Digital is very fast logic simulator. About 500r tics per second on average CPU. But not good for debugging like Logisim where you can pause simulation and check test points on signal “rails”.


#7

I was just about to go try Digital. Can’t get Logisim working with the TinyFGPA… I don’t think it supports lattice chips (In chip properties you have to select the chip brand). I’ll see if i can get ahold of the developers of logisim-evolution.


#8

Awesome! Digital exports perfectly. Sucks that Logisim makes you go through all that.


#9

is very fast logic simulator. About 500r tics per second on average CPU. But not good for debugging like Logisim where you can pause simulation and check test points on signal “rails”.

Digital provides a “Break” component that allows debugging: If this component is connected to a signal, you can run the simulation until a rising edge is detected.


#10

Didn’t expect to see you here! Thanks for the awesome work on Digital!


#11

Thanks for the awesome work on Digital!

You’re welcome. :smiley:


#12

Thank you for your reply! Big thanks to your work!
I’d tried to put Break on schematic and it isn’t work as claimed. Documentation said that work only with your CPU when it run with assembler tool.

May be things are changed since v0.21. I’ll try it later.
Again many thanks for your work.


#13

I’d tried to put Break on schematic and it isn’t work as claimed. Documentation said that work only with your CPU when it run with assembler tool.

The function of the “Break” component has never changed. When used in a circuit, a “Run to Break” button in the toolbar between “Run” and “Stop” is enabled. This button clocks the circuit to the rising edge of the break input. But maybe the documentation is a bit unclear.