UART Component and UART hub


So I’m working on a UART component for the TinyFPGA. I know that there probably are free IPs out there already, but its a bit of fun. So far I’ve got a TX component that just needs to be stitched together and I’m going to start work on the RX component tomorrow. I’ll put what I have up on github: The idea would be to wrap it in a nice (WISHBONE compliant?) package.

Also, I’m always annoyed by not having enough UARTs on my micros so the whole project will be a UART hub to connect to a micro or computer. A one byte address would be used to select a port and then traffic would continue until the bus is released. Its a thought anyways.

Parts of this project can hopefully be reused for the SPI components.

Any ideas, comments? Is a UART hub something others might find useful?


This would be great! I think if you create modules with the right interfaces you will provide a lot of useful and reusable components. For example:

  • 8-bit to serial data tx module
  • rx serial to 8-bit data module
  • 8-bit FIFO buffers (maybe the host interface is faster than the slave UART interfaces)
  • Wishbone UART controller that communicates with the 8-bit interfaces of the previous modules
  • See wb_bus.v for a Wishbone bus implementation that can connect multiple slaves
  • SPI slave to Wishbone master module
  • UART to Wishbone master

If you do this, then your code will be reusable in three big ways:

  1. Other Verilog modules can take advantage of the low-level 8-bit tx and rx interface
  2. Soft CPU cores can take advantage of the Wishbone interface
  3. External microcontrollers can take advantage of the SPI or UART interfaces

As for Wishbone, I’ve been using the Wishbone B4 Spec.


This is a funny thread, because it’s exactly what I’m working on.

I have a design, “FlyingPi”-- which is a hat for the raspberry pi with power supply, SPI sensors, and a microcontroller for timer resources and serial-- that is a drone autopilot. It works and flies and everything, but slave SPI on a microcontroller is always marginal and the protocol is a bit weird as a result, and there’s not enough UARTs. So I’m planning on revving it to use ICE40 in place of the cortex M0 for more versatility.

I’ve taken the exact approach you’ve suggested, as it turns out. I have a SPI master->asynchronous bus master bridge, then an asynchronous bus slave->wishbone master bridge.


BTW with a trivial wishbone slave it currently closes worst case timing at >192MHz; SPI needs to be 1/4th the speed of the main clock domain or less. 172 cells, 32 PLBs.


Wow thats awesome, can you share the code so we can get it up?


For now it’s here--

No UARTs etc, yet.

Edit to note: to try it out on hardware, at the very least you’ll need a PLL to generate the fast clock. (I have no tangible test setup now, but feedback of how well this works would be much appreciated!)


Ok so the code is up and the module works. It doesnt seem to sythesize quite right because of some bug in the code. It does work on the part, however. If somebody could take a look and offer some suggestions, it would be appreciated. I’m going to work on wrapping a wishbone interface around it next.

More details on my issue: I get a new_data signal from the recieve module, but the tx module doesnt seem to grab it quite right. So I inserted a sort of latch, but now I’m getting a logic loop error and a 0MHz suggested clock speed. I can’t find a solution without breaking the module.


Are you using Lattice icecube2 or icestorm for synthesis? Also, which simulator are you using? I’ll try and take a look at it later tonight.


I use icestorm and I dont use a simulator. I kinda figured it out. Its a quirk of yosys. When a latch is used it gives up on timing and states a logic loop is present.

Now all i need to figure out is how to avoid using a latch when its the best tool for the job.