Verilator with primitives


I am making a UART and for the data bus I use the SB_IO primitive ([Solved] Help getting bidirectional pins (inout) to work (BX)).
To troubleshoot my design, I wanted to try to use Verilator. However, when invoking it it gives the error:

Cannot find file containing module: 'SB_IO' 

Is this because you cannot use the primitives with Verilator?



I believe that the normal way of solving these type of issues in verilog is to use ifdef statements.
Here is an example

In many cases (like pll) is might be required to implement a stub in verilog