Went looking for a shift register to re-use. Is there a pip or brew equiv for Verilog?


#1

I have a circuit I’d like to simulate. In real life, some of the parts will be discrete (off FPGA) components - like e.g., a shift register - connected to a TinyFPGA BX. For simulation, I wanted to find a Verilog implementation of a shift register.

Acknowledging that it wouldn’t be hard to implement a shift register myself, as someone new to FPGA, I am wondering if, short of just Googling for GitHub repos (such as https://github.com/parallella/oh) if there was anything like pip for python but for Verilog or brew for Mac but for ICE40LP8K.


#2

FuseSoc claims to be a package manager for FPGAs - https://fusesoc.readthedocs.io/en/master/

Is it an input or output shift register you are using?

Is there a specific chip you want to emulate?


#3

Hi, Lawrie:

Thank you - for two things:

  1. Narrowly, thanks for the pointer to FuseSoc. It’s along the lines of what I was thinking, but (from commit activity and contributors) doesn’t appear particularly active. I think it more likely for something that comes from a community like this to get some traction. While I’m hardly qualified as an FGPA designer, if I make something I think useful to others, I’ll put it on github and post here. If this becomes a pattern, then doing a little bit of tooling work to make it easy to find and install is something I’d be glad to tackle.

  2. More broadly, thanks for all you do here, Lawrie. I’ve found your posts very helpful. I’m grateful.

With warm regards,

Dan


#4

Hi,

I have looked at a few projects that try to make reusable components or are able to generate full systems. The main problem IMHO is that that languages that are currently used “for real” e.g. verilog and VHDL are to low level and interfaces are basically not defined. It means that any attempt ( see opencores) at creating reusable components is kinda hopeless with these technologies. (there are some well known interface like wishbone that can help here but those are not the things you normally start with a developer.

I know of 3 systems
LITEX:
Python (migen) based system to create hardware “easily” and this is true. with Litex, the active community around it and the many examples it is trivial to create a full system and add your little pieces of code.
The bad news is that the syntax for “the low level stuff” is not very elegant and you kinda have to know both python and verilog/vhdl to understand what you are doing. Still it has been one of the more productive systems I tried and keep using(it is mostly code generation)

A system that is more seriously designed to be a real language and provide the high level abstractions you are looking after is SpinalHDL. it is know for the configurable VexRiscv core. The main problem here is adoption and there are not so many cores available in this language but still recently discovered

https://github.com/SpinalHDL/SaxonSoc that I did not yet try.

For short: The real fun and basics and understanding of FPGA’s is best experienced using verilog/VHDL have a look a the example code from Lawrie on github!
If you want some help and are practically oriented (e.g. have a project you just want to get done) use litex.
If you are in here for “improving the world” perhaps that SpinalHDL is something for you.