What does Diamond do?


#1

I know I’ve asked much the same question before but it still puzzles me.
If I want a counter that runs from 0 to h31F inclusive, I know that I can generate a ‘terminal count’ signal by ANDing together bits 9,8,4,3,2,1 and 0*. The obvious thing to do in Verilog is “counter==10’h31F”… but will that generate a circuit that tests bits 7, 6 and 5 against 0? Does it matter? In simple programmable logic with an AND array followed by an OR array I guess it wouldn’t.

*If I were doing it with 74xx chips I’d proably be stingy and AND bits 9,8 and 5 together to generate an asynchronous reset :blush:.


#2

As far as I know, when you use one of the equality or inequality operators, most synthesis tools will create a comparator the length of the bit vectors. Most FPGAs have carry-chains that are optimized for addition, subtraction, and comparison. These carry chains require all the bits to be physically aligned in the FPGA fabric.

For more information checkout the MachXO2 datasheet: http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf

The MachXO2 logic is made up of PFUs (programmable function units):

Each of the PFUs contains 8 4-input lookup tables and 8 data flops along a high-speed carry chain divided into 4 slices. The slices look something like this according to the datasheet:

You can see the carry-chain goes right through all the slices in the PFU. Multiple PFUs can also be chained together for carry-chain functions longer than 8-bits.


#3

I think that’s about how far I’d got through the datasheet :smile:
Oh, well, I have yet to run out of space in my A1…
I wonder how many LUT4s would be needed for Conway’s Life…