I know I’ve asked much the same question before but it still puzzles me.
If I want a counter that runs from 0 to h31F inclusive, I know that I can generate a ‘terminal count’ signal by ANDing together bits 9,8,4,3,2,1 and 0*. The obvious thing to do in Verilog is “counter==10’h31F”… but will that generate a circuit that tests bits 7, 6 and 5 against 0? Does it matter? In simple programmable logic with an AND array followed by an OR array I guess it wouldn’t.
*If I were doing it with 74xx chips I’d proably be stingy and AND bits 9,8 and 5 together to generate an asynchronous reset .